Semiconductor Engineering

Roadmap for Open-Source Chiplet-Based RISC-V Systems For HPC and AI (ETH Zurich, Univ. of Bologna)

A new technical paper titled “Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond” was published by researchers at ...
GitHub

Mojo-V: Secret Computation for RISC-V

Mojo-V (pronounced “mojo-five”) is a new RISC-V extension that introduces privacy-oriented programming capabilities for RISC-V. Mojo-V implements secret computation, enabling secure, efficient, and ...
Hackaday

Wear This RISC V, RPN Calculator Watch For Maximum Nerd Cred

Once upon a time, owning a calculator watch was the epitome of cool. Well, for a very specific subset of the population with ...
IEEE

RTL to GDSII: Design and Physical Implementation of a 32-bit RISC-V Floating-Point Co-Processor Using Verilog and Cadence Tools

Abstract: The paper presents the RTL-to-GDSII implementation of a 32-bit RISC-V floating-point co-processor in Verilog and standard Cadence tools. The co-processor adheres to IEEE 754 on all ...
IEEE

Design and Implementation of a NTT Accelerator Based on RISC-V for PQC Kyber

RISC-V, as a new generation open-source Reduced Instruction Set Computing (RISC) architecture, has the advantages of low power consumption, small footprint, and high performance. Especially, RISC-V ...
GeekWire

Survey: Two-thirds of AI-native startups let AI write most of their code

[Editor’s Note: This guest post is by Marcelo Calbucci, a longtime Seattle tech and startup community leader.] This month, I ran a survey with early-stage founders from Seattle-based Foundations about ...
EDN

The next RISC-V processor frontier: AI

The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...