Semiconductor Engineering

Roadmap for Open-Source Chiplet-Based RISC-V Systems For HPC and AI (ETH Zurich, Univ. of Bologna)

A new technical paper titled “Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond” was published by researchers at ...
IEEE

AI Edge Processor Using RISC - V Instruction Set Architecture Design

Abstract: The paper explores the design principles, architectural customizations and applications of an AI edge processor leveraging the RISC-V Instruction Set Architecture (ISA). It emphasizes ...

Inside Snapdragon X2 Elite’s Oryon: The CPU challenging Intel, AMD and Apple

At Qualcomm’s Snapdragon X2 Elite architecture deep dive, Pradeep Kanapathipillai takes his seat with the calm confidence of ...
EE World Online

A practical guide to microcontroller structure and performance factors

Microcontroller units (MCUs) are single-chip computers optimized for performing embedded computing tasks like controlling a ...
IEEE

RV-CURE: A RISC-V Capability Architecture for Full Memory Safety

Abstract: Memory-safety violations remain persistent in the real world. Although a tagged-pointer concept has demonstrated significant practical potential, prior work has shown scalability limitations ...
Electronic Specifier

Advance RISC-V ecosystem for automotive

HighTec EDV-Systeme announces a partnership with Quintauris, the company founded as a single source to enable compatible RISC-V-based products. This partnership brings together HighTec’s expertise in ...