About SiFive SiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture.

Andes’ fifth generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, ...

As part of the collaboration, Fractile will integrate Andes Technology’s high-performance RISC-V vector processor with its own groundbreaking in-memory computing architecture via ACE.

(1) A computer architecture that performs more than one operation at the same time. See multicore, multithreading, GPGPU, pipeline processing and vector processor. (2) Using multiple computers ...

The Vector Processing Unit (VPU) of the AX45MPV implements RISC-V Vector Extension (RVV) version 1.0. It. It supports configurations of up to 1024-bit vector width (VLEN) and datapath width (DLEN).