EDN

Synopsys adds testbench features to VCS

SANTA CRUZ, Calif. — Evolving its VCS Verilog simulator into a more complete verification environment, Synopsys this week (May 25) is announcing a new VCS release with added testbench capabilities. It ...
Design-Reuse

Synopsys Advances VCS Solution by Adding Assertion IP Library and Native Testbench Support for SystemVerilog

Latest version of the VCS® solution speeds standards-based verification by unifying SystemVerilog and SystemCâ„¢ languages in a single tool MOUNTAIN VIEW, Calif., May 31, 2005-- Synopsys, Inc. (Nasdaq ...
Design-Reuse

Synopsys Introduces VCS Verification Library to Speed Verification by Up to 5X

Verification IP Product Combines with Advanced Methodologies and Tools to Deliver a High-Performance Integrated Verification Environment MOUNTAIN VIEW, Calif. -- Sept. 26, 2005-- Synopsys, Inc.
EDN

Synopsys fields dual-language simulation, tweaks VCS

MOUNTAIN VIEW, Calif. — Synopsys Inc. this week joins the ranks of vendors offering “dual-language” simulation with both VHDL and Verilog. But what Synopsys is actually providing is a fast interface ...