EDN

Synopsys carefully converts customers to verification tool

SAN MATEO, Calif. — Synopsys Inc. hopes to hold on to a slight lead in the formal verification market as it moves customers from the Design Verifyer tool to its internally developed Formality ...
Design-Reuse

Issues lurk behind formal equivalence checking

SAN MATEO, Calif. - Formal equivalence checking is one of those silver bullets that comes along every so often in design flow evolution. It gives you the ability to transform a design from one level ...
EDN

Synopsys Announces Formal Verification Tool

Magellan Combines Formal Verification Engines with VCS to Find Deep Corner-Case Bugs and Enable Design for Verification MOUNTAIN VIEW, Calif.–May 12, 2003–Synopsys, Inc., the world leader in ...
Electronic Design

Xilinx And Synopsys Collaborate On Tool Flow For Platform FPGAs

Time-saving verification tools have been added to an advanced tool flow for high-end FPGA design. The flow, a collaboration between Xilinx Inc. of San Jose and Synopsys Inc. of Mountain View, Calif., ...