Electronics Weekly

How to move design algorithms to the FPGA

There are many types of designs being put into FPGAs today, but one type of design stands out – image and signal processing algorithms – because of its significant role in providing product ...
EDN

PLATFORMS: FPGA-based tools rev key algorithms

Austin, Texas — DRC Computer Corp. and software partner Celoxica Ltd. have developed an FPGA-based coprocessor module and software development tools that accelerate key algorithms. The DRC Coprocessor ...
EDN

Inside DSP on Tools: FPGA Tools Bridge Gap Between Algorithm and Implementation

Increasingly FPGAs are being used to perform signal-processing tasks, particularly in computationally demanding application areas such as video processing and communications. Their massive parallelism ...
Design-Reuse

FPGA algorithm tunes gray, color images

For both gray-scale and color image applications in an FPGA, we have implemented block truncation coding (BTC), a lossy image-compression algorithm with proven value in applications that don't require ...
MarketWatch

MicroCloud Hologram Inc. Improves Grover Algorithm to Achieve Dynamic Multi-Mode Search, Breakthrough in Quantum Circuit Simplification and FPGA Reconstruction

The MarketWatch News Department was not involved in the creation of this content. SHENZHEN, China, Oct. 23, 2025 /PRNewswire/ -- MicroCloud Hologram Inc. (NASDAQ: HOLO), ("HOLO" or the "Company"), a ...
Nature

Hardware Architecture for Cryptographic Algorithms on FPGA

Field Programmable Gate Arrays (FPGAs) have emerged as a versatile platform for implementing cryptographic algorithms, offering a balance between flexibility, performance and energy efficiency. Recent ...
Design-Reuse

Altera FPGAs Achieve Compelling Performance-per-Watt in Cloud Data Center Acceleration Using CNN Algorithms

San Jose, Calif., —February 23, 2015—Altera Corporation (NASDAQ: ALTR) today announced Microsoft (NASDAQ: MSFT) is using Altera Arria® 10 FPGAs (field programmable gate arrays), to achieve compelling ...
TechRepublic

FPGA Implementation of a Compact AES Algorithm with S-Box Optimization

In this paper, the authors propose a compact AES (Advanced Encryption Standard) algorithm to achieve less slice consumption of FPGA. Proposed design is based on iterative round looping architecture. S ...
Electronics Weekly

VMetro FusionXF FPGA development kit for embedded DSP systems

VMetro’s FusionXF FPGA development kit is targeted at reducing the design time and optimizing the performance of complex FPGA and PowerPC processing systems. It aids in the development of their FPGA ...
New Electronics

Microchip releases C++ synthesis suite for PolarFire FPGA algorithm development

Microchip Technology has added an HLS design workflow, called SmartHLS, to its PolarFire FPGA families to allow C++ algorithms to be directly translated to FPGA-optimised Register Transfer Level (RTL) ...